1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device with a TSV and a shelter.
2. Description of the Prior Art
In modern society, the micro-processor system comprised of integrated circuits (IC) is a ubiquitous device, being utilized in such diverse fields as automatic control electronics, mobile communication devices and personal computers. With the development of technology and the increasingly imaginative applications of electrical products, the IC device is becoming smaller, more delicate and more diversified.
As is well known in the art, an IC device is produced from dies that are fabricated by conventional semiconductor manufacturing processes. The process to manufacture a die starts with a wafer: first, different regions are marked on the wafer; second, conventional semiconductor manufacture processes such as deposition, photolithography, etching or planarization are used to form needed circuit trace(s); then, each region of the wafer is separated to form a die and packaged to form a chip; finally, the chip is attached onto a board, for example, a printed circuit board (PCB), and the chip is electrically coupled to the pins on the PCB. Thus, each of the programs on the chip can be performed.
In order to evaluate the functions and efficiency of the chip and increase the capacitance density to accommodate more IC components in a limited space, many semiconductor package technologies are built up by stacking each die and/or chip, for example, Flip-Chip technology, Multi-chip Package (MCP) technology, Package on Package (PoP) technology and Package in Package (PiP) technology. Besides these technologies, a “Through Silicon Via (TSV)” technique has been well developed in recent years. TSV can improve the interconnections between chips in the package so as to increase the package efficiency.
The first step to fabricate a TSV is to form a via on a wafer by an etching or a laser process, then fill the via with copper, polycrystalline silicon, tungsten, or other conductive material; next, the chip is thinned and the chips are packaged or bonded to form a 3D package structure. By using the TSV technique, there can be a shortest interconnection route between the chips. So, with comparison to other technologies, TSV has the advantages of fast-speed, less noise and better efficiency, and therefore looks set to become one of the most popular technologies in the future.
FIG. 1 illustrates two conventional stacking dies with TSV. As shown in FIG. 1, die 1 comprises a substrate 11, with a plurality of metal interconnect layers 13 disposed on the substrate 11. The metal interconnect layers 13 horizontally and vertically connect some active or passive components (not shown) within die 1 and further couple to a contact pad 15. A plurality of TSVs 14 are disposed in the substrate 11, and each TSV 14 penetrates through the substrate 11 so as to connect upward to the metal interconnect layers 13 and downward to a solder ball 16.
Die 2 comprises: a substrate 21, a plurality of metal interconnect layers 23, a plurality of TSVs 24, a plurality of contact pads 25 and a plurality of solder balls 26, wherein the relative position of each component is the same as in die 1. When stacking die 1 and die 2, the solder balls 26 of die 2 are electrically coupled to the contact pads 15 of die 1, making die 1 and die 2 electrically interconnect with each other to form a stable stacking structure. It is understood that die 1 could connect downward to a package substrate or a PCB (not shown) with the solder ball 16 for an outer power supply or a signal input/output. Similarly, die 2 could connect upward to another die (not shown) with the contact pad 25 to perform a multi-layer package.
FIG. 2 illustrates a sectional diagram of a conventional die with a TSV. As shown in FIG. 2, die 1 comprises: a substrate 11, a plurality of metal interconnect layers 13, a plurality of TSVs 14, a power distribution layer 18 and a contact pad 15. The metal interconnect layers 13 are disposed on the substrate 11 and horizontally and vertically connect some active or passive components (not shown) within die 1. Each TSV 14 penetrates through the substrate 11 and connects upward to the metal interconnect layers 13 and is open downward to a bottom surface of the substrate 11. An outer signal is transmitted from the TSV 14 to the metal interconnect layer 13.
Referring to the area A in FIG. 2, die 1 further comprise a circuit area 17. The circuit area 17 connects to the metal interconnect layer 13 and includes many semiconductor active components such as transistors or memories, or many passive semiconductor components such as inductors or resistors that can carry out electronic programs. The area A shows a TSV 14 acting as a “signal pin”, which means when an outer signal enters the TSV 14, it will pass through the metal interconnect layer 13 and reach the circuit area 17, then, after the circuit area 17 finishes the electronic program, the signal transmits to another metal interconnect layer 13, hence completing the program.
The area B shows a TSV 14 acting as a “power pin” which means the TSV 14 is coupled to a power supply. As a result, the TSV 14 as a power pin transmits more current than when it acts as a signal pin. For better transmission efficiency, a thicker and less-resistant power distribution layer 18 is disposed on the upper portion of the die 1. With the metal interconnect layer 13 that couples the TSV 14 and the power distribution layer 18, the power supply can conduct from the TSV 14 to the power distribution layer 18 for intra die power distribution.
However, when the TSV 14 acts as a power pin, the current conducted through the metal interconnect layer 13 is massive, thereby causing serious electromagnetic interference (EMI) to adjacent circuits, for example, the metal interconnect circuit 13 or the circuit area 17 in area A. This is an urgent problem to be resolved.
Therefore, it is necessary to provide a semiconductor device to prevent EMI in adjacent circuits caused by massive currents when TSV acts as a power pin